1. general description the 74hc00; 74hct00 is a quad 2-input nand gate. inputs include clamp diodes. this enables the use of current limiting resistors to interface inputs to voltages in excess of v cc . 2. features and benefits ? input levels: ? for 74hc00: cmos level ? for 74hct00: ttl level ? complies with jedec standard no. 7a ? esd protection: ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v ? multiple package options ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c 3. ordering information 74hc00; 74hct00 quad 2-input nand gate rev. 7 25 november 2015 product data sheet table 1. ordering information type number package temperature range name description version 74hc00d ? 40 ? c to +125 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74hct00d 74hc00db ? 40 ? c to +125 ? c ssop14 plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 74hct00db 74hc00pw ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74hct00pw 74HC00BQ ? 40 ? c to +125 ? c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 ? 3 ? 0.85 mm sot762-1 74hct00bq downloaded from: http:///
? nexperia b.v. 2017. all rights reserved 74hc_hct00 all information provided in this document is subject to legal disclaimers. product data sheet rev. 7 25 november 2015 2 of 15 nexperia 74hc00; 74hct00 quad 2-input nand gate 4. functional diagram 5. pinning information 5.1 pinning fig 1. logic symbol fig 2. iec logic symbol fig 3. logic diagram (one gate) p q d $ < % $ < % $ < % $ < % p q d p q d $ % < (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 4. pin configuration so14 and (t)ssop14 fig 5. pin configuration dhvqfn14 + & |